In computer architecture applications, it is often necessary to compute the sum of two N-bit numbers while also adding or subtracting a 2k constant (where k<N) to or from the recently computed sum of the same two N-bit numbers. This situation often arises more specifically in memory address calculation during load and store operations, where memory calculations such as A+B, A+B+8 and A+B−8 are performed (where, e.g., k=3, and thus, 23=8). Because the speed of memory accesses often limits the speed of a computer, the speed of the computation of these calculations is typically a primary speed limitation of computer processing units (CPUs). Conventional approaches used to calculate A+B, A+B+2k and A+B−2k are often either slow due to serially producing the results or relatively large (and power consuming) by duplicating adder hardware.